Post-Silicon and Runtime Verification for Modern Processors
Post-Silicon and Runtime Verification for Modern Processors by Ilya Wagner, published by Springer US on December 3, 2010, is a comprehensive exploration of the advancements in post-silicon and runtime verification. This 224-page book provides an overview of current methodologies in verification, particularly focusing on processor pipeline design and memory subsystems. It aims to present the evolving directions in the field, highlighting both established practices and innovative solutions.
Readers will find a detailed examination of various post-silicon verification solutions that enhance the verification coverage of modern processors. The book also addresses runtime verification solutions, reflecting on their potential to ensure correctness in microprocessor-based computation. As this area of processor design is still developing, the text concludes with insights into the future of late-stage verification and its increasing significance in the processor life-cycle.
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The purpose of this book is to survey the state of the art and evolving directions in post-silicon and runtime verification. The authors start by giving an overview of the state of the art in verification, particularly current post-silicon methodologies in use in the industry, both for the domain of processor pipeline design and for memory subsystems. They then dive into the presentation of several new post-silicon verification solutions aimed at boosting the verification coverage of modern processors, dedicating several chapters to this topic. The presentation of runtime verification solutions follows a similar approach. This is an area of processor design that is still in its early stages of exploration and that holds the promise of accomplishing the ultimate goal of achieving complete correctness guarantees for microprocessor-based computation. The authors conclude the book with a look towards the future of late-stage verification and its growing role in the processor life-cycle.
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